EGR 234 |
Digital Logic Design |
Fall 2010 (Sophmore) |
5 - Digital Logic Circuit Design Using the DE2 Board |
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EGR 234 |
Digital Logic Design |
Fall 2010 (Sophmore) |
6 - Hex-to-Seven Segment Decoder Design Using VHDL |
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EGR 234 |
Digital Logic Design |
Fall 2010 (Sophmore) |
7 - Modular Approach for Adder Implementation |
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EGR 234 |
Digital Logic Design |
Fall 2010 (Sophmore) |
8 - Modular Approach for a Double-Digit BCD Adder |
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EGR 234 |
Digital Logic Design |
Fall 2010 (Sophmore) |
9 - Arithmetic and Logic Unit Design |
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EGR 234 |
Digital Logic Design |
Fall 2010 (Sophmore) |
10 - Digital Clock Using Counters and VHDL |
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EGR 333 |
Electronics I |
Fall 2011 (Junior) |
4 - Rectifier Circuits |
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EGR 333 |
Electronics I |
Fall 2011 (Junior) |
5 - MOSFET Measurement and DC Analysis |
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EGR 322 |
Microcontroller System Design |
Spring 2012 (Junior) |
5 - Pulse Width Modulation (PWM) |
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EGR 322 |
Microcontroller System Design |
Spring 2012 (Junior) |
6 - Digital Clock Using PSoC Timer and LCD Tool Box |
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EGR 322 |
Microcontroller System Design |
Spring 2012 (Junior) |
7 – Reference Multiplexer and Programmable Gain Amplifier |
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EGR 431 |
Microcontroller System Design |
Spring 2012 (Junior) |
4 – QET DCMCT Speed Control with a PI Controller |
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EGR 400 |
Advanced Digital System Design Using FPGAs |
Fall 2012 (Senior) |
1 – Gate-Level Binary Decoder |
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EGR 400 |
Advanced Digital System Design Using FPGAs |
Fall 2012 (Senior) |
2 – Barrel Shifter Design |
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EGR 400 |
Advanced Digital System Design Using FPGAs |
Fall 2012 (Senior) |
3 – Enhanced Stopwatch Design |
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EGR 400 |
Advanced Digital System Design Using FPGAs |
Fall 2012 (Senior) |
4 – Alternative Debouncing Circuit |
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